The present invention relates to a semiconductor device, and particularly to a semiconductor device including a plurality of semiconductor chips and a wiring substrate over which the plurality of semiconductor chips are mounted.
Techniques for integrating a plurality of semiconductor chips and a plurality of semiconductor packages into one package include SiP (Silicon in Package). Examples of the SiP include one in which a plurality of semiconductor chips and a plurality of packages are mounted over a wiring substrate and provided as a semiconductor device. In this case, the wiring substrate has a main surface (first main surface) facing the semiconductor chip mounted thereover and a main surface (second main surface) facing a user's (customer's) substrate over which the semiconductor device is mounted. Over the first main surface, a plurality of external terminals (first external terminals) to be connected with the semiconductor chips are provided. Over the second main surface, a plurality of external terminals (second external terminals) to be connected with the user's substrate are provided. The wiring substrate includes wiring a layer interposed between the first and second main surfaces. Metal wires in the wiring layer provide electrical connection between the first external terminals and/or between the first and second external terminals.
For example, by connecting the first external terminals using the metal wires, it is possible to omit wiring lines connecting the semiconductor chips from the user's substrate and reduce a load on the user. It is also possible to achieve a higher-speed operation.
On the other hand, it has been performed to combine, e.g., a plurality of hard macros having different functions to configure a semiconductor chip.
A technique which combines hard macros to configure a semiconductor chip is described in, e.g., each of Patent Documents 1 to 3.